IDA Processor module segmentation

[Git]

CPU module. Code sits in the eprom. Operands that are in RAM are addressed by the operand addressing mode. For example, VARA += VARB :

Code segment :

000 MOV R0, #VARA ; R0 contains address of RAM variable VARA
002 MOV R1, #VARB ; R1 contains address of RAM variable VARB
004 MOV A, @R0 ; Get contents of VARA into accumulator
005 ADD A, @R1 ; Add contents of VARV to accumulator
006 MOV @R0, A ; Put results back into VARA

Data Segment :
000 VARA: .DS 1 ; Reserve 1 byte in RAM for VARA
001 VARB: .DS 1 ; Reserve 1 byte in RAM for VARB

It's a little more complicated in that the registers are in RAM and take 0x00 to 0x17, so RAM variables can start at 0x17. Makes no difference to the problem in hand though.

Git